As clock rates have increased, the duration of signal rise and fall times has decreased. Inside an IC design where total length is an issue, this causes some of the signals to have transmission line effects. At the PCB level, these same signal speeds result in far more transmission line effects due to the lengths being orders of magnitude larger. Increasingly, a larger percentage of the total nets on a design have both physical and electrical constraints. In older systems where only 10% of the nets on a design had tight constraints, it was possible to route them first or to route them multiple times in an almost random fashion in order to find a solution. In the current state-of-the-art PCB designs, 90% of the nets have both electrical and physical constraints. Therefore, it is impossible to route them all first. Further, iterative processes are unlikely to succeed without taking a global view.
Additionally, there has been a continual increase in the number of pins per package. This has resulted in more buses and hence an increased need for matched track lengths within sets of nets. It is common to require each net in a bus to have the same length as all other nets in the bus to within less than 0.01% tolerance. This means that all of the paths of all of the nets in the bus must travel side-by-side on the same layers. Since these buses can reach 64-bits, they occupy a considerable amount of area on the layer
For today's leading-edge, high-speed PCB designs, routing is always done manually by a team of highly experienced PCB designers. Each segment of each track is laid down individually. That is, all of the planning goes on inside the head of the designer. Presently, there is no means to communicate a designer's design plans to an autorouter. As a result, designs that could have been autorouted in an hour without the need to meet electrical constraints take a man-year or more for PCB designers to manually route to meet all of the required physical and electrical constraints.
There is no autorouter on the market today that can autoroute dense designs where 90% of the nets have both physical and electrical constraints.
Present PCB routing systems use a geometry-based routing engine to route individual pin pairs. Generally, they allow crossovers and other violations of physical design rules and then try to eliminate the crossovers and violations by performing multiple iterations. In these systems, each net is considered based on its own design rules and ignores the design rules of all other nets unless they are directly related to the design rules for the current net. Thus, each iteration is a geometric solution with a set of known design rule violations that is derived from the previous iteration which was also a geometric solution with a set of known design rules violations. The convergence process is based on finding new paths for individual nets, one at a time, that result in fewer overall design violations. There is no global planning or solution finding mechanism. When there are many electrical constraints, this process ceases to converge long before a solution can be found or converges so slowly, as to be impractical.
In the digital IC realm, there are many autorouting products that have used global routing for years. Current routers start with a global routing solution and then proceed in stages to route smaller and smaller grids until a complete geometric solution has been found. However, the goal of global routing for digital IC autorouters is performance, not constraint optimization. When routing designs with 100 million gates, there are trillions of potential solutions; the autorouter only needs to find one and it needs to converge quickly on a solution.
Global routing allows the design to be abstracted to provide less detail and manage less data. Once a global solution is found, successive iterations attempt to find solutions within the confines of the global solution. At no point do these systems try to find new global solutions after a first global solution has been found. If the successive iterations do not converge on a solution, then the entire routing process fails and must be restarted. This is rarely a problem with digital IC routers, since these systems can usually insert vias and/or buffers to find a solution. In most cases, the system can also change the original problem by resizing or moving gates.
In PCB routing however, inserting new vias is frequently forbidden by the design rules; and, moving or modifying components is rarely possible. Thus, applying traditional digital IC global routing technology to PCB routing can make the routing problem worse. For PCB routing, committing to a global geometric solution before all constraints were verified at the lowest level only adds artificial constraints to a design that already has too many design constraints.
In order to solve the problem of routing designs in PCBs with many constraints, a global solution is needed that creates a global flow plan meeting all or most of the constraints and then iteratively refining it.